Design flow and modelling for a hierarchically designed RFICs with the ground plane
Naushahi, Shayan Hasan (2023-12-11)
Naushahi, Shayan Hasan
S. Naushahi
11.12.2023
© 2023 Shayan Hasan Naushahi. Ellei toisin mainita, uudelleenkäyttö on sallittu Creative Commons Attribution 4.0 International (CC-BY 4.0) -lisenssillä (https://creativecommons.org/licenses/by/4.0/). Uudelleenkäyttö on sallittua edellyttäen, että lähde mainitaan asianmukaisesti ja mahdolliset muutokset merkitään. Sellaisten osien käyttö tai jäljentäminen, jotka eivät ole tekijän tai tekijöiden omaisuutta, saattaa edellyttää lupaa suoraan asianomaisilta oikeudenhaltijoilta.
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:oulu-202312143785
https://urn.fi/URN:NBN:fi:oulu-202312143785
Tiivistelmä
Recently, Cadence Design System has launched a latest design tool, “Virtuoso RF solution”, that offers a new and efficient Radio Frequency Integrated Circuit (RFIC) design flow. The concept of “Golden” or “Master” schematic is introduced in this new design flow as whole IC design process can be handled through single design schematic which could be hierarchically designed. Using the latest design tool, it is no longer required to create additional schematic containing S-parameter blocks from the electromagnetic analysis and neither for Layout Versus Schematics (LVS) verification. Results from electromagnetic (EM) analysis can directly be brought to the golden schematic either for the whole layout or for the selected parts by creating EM extracted views.
Due to complexity in the design flow in the previous versions of RFIC design tools, RFIC designer prefers to build separate design files, i.e., one for tape-out purpose which is LVS and DRC clean version, and the other one for performing electromagnetic simulations. In addition, due to computational limitations of the design tool, the electromagnetic simulations had to be performed in piece-wise manner instead of simulating the whole design.
The purpose of this thesis is to implement and verify the new design flow offered by the Cadence environment. As a case study, new design flow is tested on multi-stage Low Noise Amplifier (LNA) that has been designed at the sub-THz frequencies (centre frequency at 290 GHz). The LNA is part of an existing RFIC chip design that consists of an on-chip antenna, LNA, and power detector. In the existing LNA design, Layout Versus Schematic (LVS) clean files were built for the tape out purpose, and separate layout files were built for performing electromagnetic simulations. The reason for having separate layout views for performing EM simulations is that multiple pins must be added on the ground plane which creates an LVS problem. The focus of this thesis is now to utilize only LVS clean design files and configure them for EM simulations. In this process, the main challenge is to accurately model the ground plane of the RFIC for the simulations purpose. The new features within the Cadence environment using new integrated EM simulator i.e., EMX are tested in this thesis and the extracted results, mainly frequency responses of the LNA, are compared with the Momentum that has been previously used. In the first stage of the thesis work, EM simulations were performed on the individual stages of the LNA and then the frequency response was measured for the cascaded blocks. In the later part, EM simulations are performed over the whole LNA design to capture the EM coupling between the stages.
Due to complexity in the design flow in the previous versions of RFIC design tools, RFIC designer prefers to build separate design files, i.e., one for tape-out purpose which is LVS and DRC clean version, and the other one for performing electromagnetic simulations. In addition, due to computational limitations of the design tool, the electromagnetic simulations had to be performed in piece-wise manner instead of simulating the whole design.
The purpose of this thesis is to implement and verify the new design flow offered by the Cadence environment. As a case study, new design flow is tested on multi-stage Low Noise Amplifier (LNA) that has been designed at the sub-THz frequencies (centre frequency at 290 GHz). The LNA is part of an existing RFIC chip design that consists of an on-chip antenna, LNA, and power detector. In the existing LNA design, Layout Versus Schematic (LVS) clean files were built for the tape out purpose, and separate layout files were built for performing electromagnetic simulations. The reason for having separate layout views for performing EM simulations is that multiple pins must be added on the ground plane which creates an LVS problem. The focus of this thesis is now to utilize only LVS clean design files and configure them for EM simulations. In this process, the main challenge is to accurately model the ground plane of the RFIC for the simulations purpose. The new features within the Cadence environment using new integrated EM simulator i.e., EMX are tested in this thesis and the extracted results, mainly frequency responses of the LNA, are compared with the Momentum that has been previously used. In the first stage of the thesis work, EM simulations were performed on the individual stages of the LNA and then the frequency response was measured for the cascaded blocks. In the later part, EM simulations are performed over the whole LNA design to capture the EM coupling between the stages.
Kokoelmat
- Avoin saatavuus [32473]