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Design and implementation of parallel memory architectures
URI:
http://urn.fi/URN:NBN:fi:bib:me:W00046079500
author
Aho, Eero
contributor
Tampereen teknillinen yliopisto
inLanguage
en
isPartOf
Fennica
name
Design and implementation of parallel memory architectures
P60049
<http://rdaregistry.info/termList/RDAContentType/1020>
Instances
-, e-book
2006 : Tampereen teknillinen korkeakoulu
Design and implementation of parallel memory architectures
URI:
http://urn.fi/URN:NBN:fi:bib:me:I00046079501
bookFormat
<http://schema.org/EBook>
isPartOf
Fennica
Valtion teknillinen tutkimuskeskus publications
name
Design and implementation of parallel memory architectures
url
<http://URN.fi/URN:NBN:fi:tty-200810021038>
View this in Finna
Design and implementation of parallel memory architectures
URI:
http://urn.fi/URN:NBN:fi:bib:me:I00046079500
datePublished
2006
description
kuvitettu
Tiivistelmä ja 10 erip.
identifier
propertyID:
FI-FENNI
value:
847647
propertyID:
FI-MELINDA
value:
000460795
propertyID:
skl
value:
fx847647
isbn
9521516895
isPartOf
Fennica
Valtion teknillinen tutkimuskeskus publications
name
Design and implementation of parallel memory architectures
numberOfPages
xix, 67, [90] s.
P60048
<http://rdaregistry.info/termList/RDACarrierType/1049>
P60050
<http://rdaregistry.info/termList/RDAMediaType/1007>
publication
location:
Tampere
organizer:
Tampereen teknillinen korkeakoulu Tampereen teknillinen yliopisto. Optoelektroniikan tutkimuskeskus
publisher
Tampereen teknillinen korkeakoulu
Tampereen teknillinen yliopisto. Optoelektroniikan tutkimuskeskus
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