RVNoC : a framework for generating RISC-V NoC-based MPSoC
Elmohr, Mahmoud A.; Eissa, Ahmed S.; Ibrahim, Moamen; Khamis, Mostafa; El-Ashry, Sameh; Shalaby, Ahmed; AbdElsalam, Mohamed; El-Kharashi, M. Watheq (2018-06-07)
M. A. Elmohr et al., "RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC," 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), Cambridge, 2018, pp. 617-621, doi: 10.1109/PDP2018.2018.00103
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https://urn.fi/URN:NBN:fi-fe2020052739317
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Abstract
With the increase in the number of cores embedded on a chip; The main challenge for Multiprocessor System-on-Chip (MPSoC) platforms is the interconnection between that massive number of cores. Networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. The proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 μW/MHz power consumption.
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