Run-to-Completion versus Pipelined : The Case of 100 Gbps Packet Parsing
Zolfaghari, Hesam; Mustafa, Haseeb; Nurmi, Jari (2021-06-07)
Lataukset:
Zolfaghari, Hesam
Mustafa, Haseeb
Nurmi, Jari
IEEE
07.06.2021
2021 IEEE 22nd International Conference on High Performance Switching and Routing, HPSR 2021
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202110117517
https://urn.fi/URN:NBN:fi:tuni-202110117517
Kuvaus
Peer reviewed
Tiivistelmä
Packet parsing is the initial step in processing of network packets. It is encountered in any environment in which packets must be processed. Examples include switches, routers, firewalls, and kernel of operating system. In recent years, there has been focus on programmable and protocol-independent packet processing hardware. The two main hardware architectures for packet processing are run-to-completion and pipelined organization of functional units. This applies to packet parsing as well. Both run-to-completion and pipelined organization have pros and cons and the debate as to which provides greater overall benefit is endless. In this paper, we consider this problem from the perspective of programmable 100 Gbps packet parsing. We will see that the pipelined parser provides 40x throughput compared to the run-to-completion architecture despite running at the same operating frequency and using the same functional units in each pipeline stage.
Kokoelmat
- TUNICRIS-julkaisut [16951]