Simplified Floating-Point Division and Square Root
Viitanen, Timo; Jääskeläinen, Pekka; Esko, Otto; Takala, Jarmo (2013)
Viitanen, Timo
Jääskeläinen, Pekka
Esko, Otto
Takala, Jarmo
Institute of Electrical and Electronics Engineers
2013
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201306261273
https://urn.fi/URN:NBN:fi:tty-201306261273
Kuvaus
Peer reviewed
Tiivistelmä
Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent research shows that floating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difficulties associated with fixed-point arithmetic. This paper investigates the effects of simplified floating-point arithmetic applied to an FMA-based floating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overflow-related errors with inexpensive exponent-manipulation special instructions.
Kokoelmat
- TUNICRIS-julkaisut [16740]