Designing of Low Power RF-Receiver Front-end with CMOS Technology

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Journal Title
Journal ISSN
Volume Title
Sähkötekniikan korkeakoulu | Master's thesis
Date
2017-10-23
Department
Major/Subject
Mikro- ja nanotekniikka
Mcode
S3010
Degree programme
NanoRad - Master’s Programme in Nano and Radio Sciences (TS2013)
Language
en
Pages
55
Series
Abstract
This thesis studies how to design ultra low power radio-receiver front-end circuit consisting of a low-noise CMOS amplifier and mixer for low power Bluetooth applications. This system is designed in 65-nm CMOS technology with the voltage source of 1.2 V, and it operates at 2.4 GHz. This research project includes the design of radio frequency integrated circuit with CMOS technology using CAD software for circuit design, layout design, pre and post-layout simulations. Firstly, brief study about both Low noise amplifier (LNA) and mixer has been done, and then the design structure such as, input matching network of LNA, noise of system, gain and linearity have been discussed. Later, next section reports simulation results of LNA, mixer and eventually their combination. Furthermore, the effect of packaging and non-ideal on-chip circuit performance has been considered and shown in comparison tables for more clarity. Finally, after the layout design, the obtained results of both post-layout and pre-layout simulations are compared and shown the stability of the design with parasitics consideration.
Description
Supervisor
Halonen, Kari
Thesis advisor
Chouhan, Shailesh Singh
Keywords
ultra low power front-end receiver, low noise CMOS amplifier, Gilbert mixer, Bluetooth, radio frequency receiver
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