Multi-output Synthesizers for Integrated Transceivers

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Journal Title
Journal ISSN
Volume Title
School of Electrical Engineering | Doctoral thesis (article-based) | Defence date: 2022-03-11
Date
2022
Major/Subject
Mcode
Degree programme
Language
en
Pages
120 + app. 88
Series
Aalto University publication series DOCTORAL THESES, 27/2022
Abstract
This thesis focuses on concepts, designs and implementations of various multi-output clocking circuits for RF front-ends in mobile terminals. A total of three experimental concepts and five evaluation designs are discussed. Two in-situ calibration concepts are shown to equalize the latencies between plural outputs in stretched multi-output arrangements. Both calibration techniques demonstrated that a digital engine can be run directly from multiple outputs while calibrating their latencies and locking the chained stages delay to the reference cycle. A third side concept of over-an-octave frequency source is presented in the form of a switched-oscillator stacked within a distributed multiplexing network for which the simulations supported the frequency coverage of the stacked oscillators. Two evaluation designs of multi-output code-to-time converters are presented in distinct implementations that eliminate the bulky arrays of passive components. The first embodiment uses active delay cells in branched chains to generate driving waveforms for a quadratures mixer in the receiver and demonstrates LO-phase shifting sufficient for practical beamsteering applications. The second all-digital embodiment with a theoretically unbounded number of delaying channels and a shared communication bus demonstrates a delay tuning range wide enough for sub-6GHz phase modulators. The third prototype design in this work is an all-digital inductor-less PLL driving the frequency multiplier. It is shown by the presented implementation that a PLL-controled ring oscillator can generate multiple phase shifted signals for the inputs of the frequency multiplier. The discussed arrangement exploits a small area and the wide tunability benefits of a sub-6GHz ring oscillator and uses programmable multiplication to translate PLL output frequency into several Gb/s data-rates, thus reducing exclusive pins for an application processor in the limited mobile space. The fourth evaluation design discussed in the thesis is delay-line based multiplier for fractional-N multiplication of the reference frequency. It is verified in the presented work that large frequency jumps can be achieved without compromising the resolution of the channel selection, which makes it possible to rapidly search for unoccupied spectrum in sub-6GHz front-ends. Furthermore, the output quantization noise after frequency multiplication can be shaped with a delta-sigma modulator and output deterministic jitter can be significantly reduced with a post-modulator. The fifth implementation presented in this work is a synthesizer of the pulse streams for multiple mixers in paralleled receiving front-ends. The thesis demonstrates that the generation of pulses can be split into waveform generation and further processing of the waveform, which supports on-chip scalability both in the number of driven mixers and output phases. Furthermore, since pulses are separately generated  close to mixers, there is no need for a synthesizer-centered layout.
Description
Supervising professor
Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
Thesis advisor
Stadius, Kari, Dr., Aalto University, Finland
Keywords
CMOS, delay line, delay-locked loop, integrated circuit design, 5G mobile communication, digital-to-time conversion, beam steering, on-chip calibration, digital control, oscillator
Other note
Parts
  • DOI: 10.1109/ECCTD.2015.7300035 View at publisher
  • [Publication 2]: T. Nieminen, T. Tikka, Y. Antonov, O. Viitala, K. Stadius, M. Voutilainen and J. Ryynänen. A 5.8-Gbps Low-noise Scalable Low-voltage Signaling Serial Link Transmitter for MIPI M-PHY in 40-nm CMOS. Journal of Analog Integrated Circuits and Signal Processing, Volume 82, Issue 1, pp. 159–169, January 2015.
    DOI: 10.1007/s10470-014-0433-7 View at publisher
  • [Publication 3]: Y. Antonov, M. Törmänen, J. Ryynänen, A. Pärssinen and K. Stadius. A 20-60GHz Digitally Controlled Composite Oscillator for 5G. In In the Proceedings of the IEEE New Generation of Circuits and Systems Conference (NGCAS), Valletta, Malta, 4 pages, 20-23 November 2018.
    Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-201901141092
    DOI: 10.1109/NGCAS.2018.8572103 View at publisher
  • DOI: 10.1109/RFIC.2016.7508268 View at publisher
  • DOI: 10.1109/ISCAS.2017.8050740 View at publisher
  • DOI: 10.1109/ECCTD.2017.8093344 View at publisher
  • [Publication 7]: Y. Antonov, M. Zahra, K. Stadius, Z. Khonsari, N. Ahmed, I. Kempi, J. Inkinen, V. Unnikrishnan and J. Ryynänen. A 3-43ps Time-delay Cell for LO Phase-shifting in 1.5-6.5GHz Beamsteering Receiver. In In the Proceedings of the IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, Canada, 4 pages, 24-27 June 2018.
    Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-201901141190
    DOI: 10.1109/NEWCAS.2018.8585704 View at publisher
  • Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS. In In the Proceedings of the IEEE European Solid State Circuits Conference (ESSCIRC), Kraków, Poland, 4 pages, 23-26 September 2019.
    Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-202001021206
    DOI: 10.1109/ESSCIRC.2019.8902864 View at publisher
  • [Publication 9]: F. Ul Haq, M. Englund, Y. Antonov, M. Tenhunen, K. Stadius, M. Kosunen, K. B. Östman, K. Koli and J. Ryynänen. A Six-Phase Two-Stage Blocker-Tolerant Harmonic-Rejection Receiver. Transactions on Microwave Theory and Techniques, Volume 68, Issue 5, pp. 1964- 1976, May 2020.
    Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-202006254163
    DOI: 10.1109/TMTT.2020.2966152 View at publisher
  • [Publication 10]: J. Lemberg, M. Martelius, E. Roverato, Y. Antonov, T. Nieminen, K. Stadius, L. Anttila, M. Valkama, M. Kosunen and J. Ryynänen. A 1.5–1.9-GHz All-Digital Tri-Phasing Transmitter with an Integrated Multilevel Class-D Power Amplifier Achieving 100-MHz RF Bandwidth. Journal of Solid-State Circuits, Volume 54, Issue 6, pp. 1517-1527, June 2019.
    Full text in Acris/Aaltodoc: http://urn.fi/URN:NBN:fi:aalto-201906203931
    DOI: 10.1109/JSSC.2019.2902753 View at publisher
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